ADSC584WCBCZ4A12

ADSC584WCBCZ4A12 is a SHARC+ dual-core DSP with arm cortex-A5. This processor is member of the SIMD SHARC family of digital signal processors (DSPs) that features Analog Devices, Inc., Super Harvard Architecture®. This floating-point processor is optimized for high performance audio/floating-point applications with large, on-chip, static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products. By integrating a set of industry leading system peripherals and memory, the Arm Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package.

• Byte, short-word, word, long-word addressed, arm cortex-A5 core
• Powerful DMA system, on-chip memory protection, integrated safety features
• Low system power across automotive temperature range
• Large on-chip L2 SRAM with ECC protection, up to 256KB on-chip L2 ROM (512KB)
• Security and protection, cryptographic hardware accelerators
• Fast secure boot with IP protection, support for arm TrustZone
• High performance pipelined FFT/IFFT engine, FIR, IIR, HAE, SINC offload engines
• AEC-Q100 qualified for automotive applications
• 450MHz processor instruction rate (max), 2 SHARC+cores, 640KB SHARC+SRAM, 1 arm core
• 349-Ball cspBGA package, -40°C to +133°C temperature range

Piezīmes

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